Timing Results: Dual 200mhz Pentium Pro

wl - write lock only
wl (rl) - write lock with a nested read lock
wl (rl wl) - write lock with nested read lock and write lock

IsWriteLock (StackBase)
wl DEBUG(NO DEBUG)
			RL		RU		Wl		WU		IS		REG	UNREG
	100/10
			7(4)		6(3)		6(6)		2(2)		2(2)		2	2
			7(4)		6(3)		6(5)		2(2)		2(2)		2	2
			7(4)		6(3)		7(5)		2(2)		2(2)		2	2
			7(4)		6(3)		6(5)		2(2)		2(2)		2	2
			
	10/10
			8(4)		6(3)		7(5)		2(2)		2(2)		2	2
			7(4)		6(3)		7(5)		2(2)		2(2)		2	2
			7(4)		6(3)		6(5)		2(2)		2(2)		2	2
			7(4)		6(3)		7(5)		2(2)		2(2)		2	2
			
	0/1
			0(0)		0(0)		11(10)	3(2)		2(2)		0	0
			0(0)		0(0)		12(12)	3(3)		2(2)		0	0
			0(0)		0(0)		14(10)	3(2)		2(2)		0	0
			0(0)		0(0)		13(10)	3(2)		2(2)		0	0
			
wl(rl) DEBUG(NO DEBUG)
	100/10
			7(4)		6(3)		5(6)		2(2)		2(2)		2	2
			7(4)		6(3)		5(7)		2(5)		2(2)		2	2
			7(4)		6(3)		5(5)		2(2)		2(2)		2	2
			7(4)		6(3)		7(6)		2(2)		2(2)		2	2
			
	10/10
			6(4)		5(2)		6(5)		2(2)		1(1)		2	2
			6(4)		5(2)		7(5)		2(2)		1(1)		2	2
			6(4)		5(2)		7(5)		2(2)		1(1)		2	2
			6(4)		5(2)		7(6)		2(2)		1(2)		2	2
			
	0/1
			1(1)		1(1)		12(11)	3(2)		1(1)		0	0
			1(1)		1(1)		12(10)	3(2)		1(1)		0	0
			2(1)		1(1)		12(12)	3(2)		1(1)		0	0
			1(1)		1(1)		12(10)	3(2)		1(1)		0	0
			
wl(rl wl) DEBUG(NO DEBUG)
	100/10
			7(4)		6(3)		4(3)		1(1)		2(2)		2	2
			7(4)		5(3)		4(3)		1(1)		2(2)		2	2
			7(4)		6(3)		3(3)		1(1)		2(2)		2	2
			7(4)		5(3)		4(3)		1(2)		2(2)		2	2
	10/10
			6(4)		5(2)		3(3)		1(1)		1(1)		2	2
			6(4)		5(2)		4(3)		1(2)		1(1)		2	2
			6(3)		5(2)		3(3)		2(1)		2(1)		2	2
			6(4)		5(2)		3(3)		1(1)		1(1)		2	2
			
	0/1
			1(1)		1(1)		6(5)		1(2)		1(1)		0	0
			1(1)		1(1)		6(5)		2(2)		1(1)		0	0
			1(1)		1(1)		6(6)		1(2)		1(1)		0	0
			2(1)		1(1)		6(5)		2(2)		1(1)		0 	0

IsWriteLock (No Stack Base)
wl DEBUG(NO DEBUG)
	100/10
			7(4)		6(3)		5(6)		4(3)		2(2)		2	2
			7(4)		6(3)		5(5)		3(3)		2(2)		2	2
			7(4)		5(3)		5(5)		3(3)		2(2)		2	2
			7(3)		6(3)		6(4)		4(3)		2(2)		2	2
			
	10/10 	
			7(4)		6(3)		6(4)		3(3)		2(2)		2	2
			7(4)		6(3)		6(4)		3(3)		2(2)		2	2
			7(4)		6(3)		5(4)		3(3)		2(2)		2	2
			7(4)		6(3)		6(4)		3(3)		2(2)		2	2
			
	0/1		
			0(0)		0(0)		10(12)	4(4)		2(2)		0	0
			0(0)		0(0)		11(9)	4(4)		2(2)		0	0
			0(0)		0(0)		10(9)	4(4)		2(2)		0	0
			0(0)		0(0)		10(9)	4(4)		2(2)		0	0

wl(rl) DEBUG (NO DEBUG) 
	100/10
			7(3)		5(3)		6(4)		3(3)		2(2)		2	2
			7(3)		5(3)		5(4)		3(3)		2(2)		2	2
			7(4)		5(3)		6(5)		3(3)		2(2)		2	2
			7(4)		5(3)		5(5)		4(3)		2(2)		2	2
			
	10/10
			6(4)		5(3)		6(4)		3(3)		2(2)		2	2
			6(4)		5(3)		5(5)		3(3)		2(2)		2	2
			6(4)		5(3)		5(5)		3(3)		2(2)		2	2
			6(4)		5(3)		5(4)		3(3)		2(2)		2	2
	
	0/1
			3(3)		3(3)		12(9)	4(4)		2(2)		0	0
			3(3)		3(3)		11(10)	4(4)		2(2)		0	0
			3(3)		3(3)		11(10)	4(4)		2(2)		0	0
			3(3)		3(3)		10(10)	4(4)		2(2)		0	0
	
wl(rl wl) DEBUG (NO DEBUG) 
	100/10
			7(4)		5(3)		4(4)		3(3)	2(2)		2	2
			7(3)		5(3)		4(4)		4(3)	2(2)		2	2
			7(3)		6(3)		4(4)		3(3)	2(2)		2	2
			6(4)		5(3)		3(4)		4(3)	2(2)		2	2
			
	10/10
			7(4)		5(3)		4(3)		3(3)	2(2)		2	2
			7(4)		5(3)		4(4)		3(3)	2(2)		2	2
			6(4)		5(3)		4(4)		3(3)	2(2)		2	2
			6(4)		5(3)		4(4)		3(3)	2(2)		2	2
			
	0/1
			3(3)		3(3)		7(6)		3(3)	2(2)		0	0
			3(3)		2(3)		6(6)		3(3)	2(2)		0	0
			3(3)		3(3)		6(6)		3(3)	2(2)		0	0
			3(3)		3(3)		6(6)		3(3)	2(2)		0	0


